Generally, a semiconductor memory device receives an external clock signal and operates by using the clock signal as reference timing of an internal operation. In particular, a synchronous DRAM of the semiconductor memory device performs data read and write operations in synchronization with an external clock signal applied from an exterior. Thus, the semiconductor memory device such as the synchronous DRAM includes a clock buffer that generates an internal clock signal for buffering the external clock signal.
The clock buffer is driven in response to a clock enable signal CKE. For example, when the clock enable signal CKE is at a high level, the clock buffer is driven to generate the internal clock signal by buffering the external clock signal. However, when the clock enable signal CKE is at a low level, since the clock buffer is not driven, the internal clock signal is not generated.
Meanwhile, if the clock enable signal CKE is shifted from the low level to the high level, since driving of the clock buffer is determined according to setup/hold time, the internal clock signal may be generated or vice versa. In a state in which generation of the internal clock signal is not clear as described above, a command signal for an internal operation of the semiconductor memory device should not be generated.
However, in the case of the conventional command signal generating circuit (not shown), when generation of the internal clock signal is not clear, the command signal may be generated. Hereinafter, the details will be described with reference to FIG. 1.
As illustrated in FIG. 1, if the clock enable signal CKE is shifted from the low level to the high level, a chip select signal CSB is enabled at a low level during a predetermined interval. During the interval in which the chip select signal CSB is enabled at the low level, when first to fourth control signals CA<0:3>, which control the internal operation of the semiconductor memory device, are at a low level “X”, a MRW (mode register write) command signal generated from the command signal generating circuit is enabled at a high level.
In the conventional command signal generating circuit as described above, if the first to fourth control signals CA<0:3> are at a low level in a state in which the chip select signal CSB is shifted to the low level by the clock enable signal CKE shifted to the high level, the MRW command signal is enabled at the high level. During the interval in which the clock enable signal CKE is shifted from the low level to the high level as described above, since generation of the internal clock signal is not clear, the MRW command signal may cause an abnormal operation of the semiconductor memory device.